| ACE |
AXI Coherency Extensions (another extension to AMBA and AXI) |
| ADC |
Analog to Digital Converter |
| ADE |
Analog Design Environment - a Cadence tool or analdesign |
| ADF |
ASIC Design Flow (digital) |
| AES |
Advanced Encryption Standard |
| AFE |
Analog Front End |
| AGC |
Automatic Gain Control |
| AGU |
Address Generation Unit |
| AHB |
Advanced High-performance Bus |
| AI |
Artificial Intelligence |
| AIB |
Advanced Interface Bus |
| ALU |
Arithmetic Logic Unit |
| AM |
Amplitude Modulation |
| AMBA |
Advanced Microcontroller Bus Architecture |
| AMS |
Analog Mixed Signal |
| APB |
Advanced Peripheral Bus |
| API |
Application Programming Interface |
| APLL |
Analog Phase Locked Loop |
| APR |
Automatic Place and Route |
| AR |
Address Register |
| ARNS |
Aeronautical Radio Navigation System band - radio frequencies used for airplane navigation |
| ASA |
American Semiconductor Academy |
| ASB |
Advanced System Bus (predecessor to AHB, not recommended for new designs) |
| ASCII |
American Standard Code for Information Interchange |
| ASIC |
Application Specific Integrated Circuit |
| ASSP |
Application Specific Standard Product |
| AST |
Abstract Syntax Tree |
| AWS |
Amazon Web Services (cloud service) |
| AXI |
Advanced eXtensible Interface (an extenstion to AMBA) |
| AXI4 |
Advanced eXtensible Interface |
| BAG |
Berkeley Analog Generator |
| BEOL |
Back End Of the Line |
| BER |
Bit Error Rate |
| BF |
Beam Forming |
| BHT |
Branch History Table |
| BIST |
Built-In Self Test |
| BIT |
Built-In Test |
| BLE |
Bluetooth Low Energy |
| BOC |
Binary Offset Carrier - enhancement to GPS’s basic BPSK encoding |
| BOOM |
Berkeley Out of Order Machine |
| BPF |
Bandpass Filter |
| BPSK |
Binary Phase Shift Keying |
| BRAM |
Block Random Access Memory |
| BSIM4 |
device models for sub-100nm CMOS transistors |
| BTB |
Branch Target Buffer |
| BW |
BandWidth |
| C |
/A Coarse Acquisition - GPS civilian resolution system |
| C |
/A Civilian Access - GPS civilian resolution system, i.e. coarse access |
| C |
/A Clear Aquisition - GPS civilian resolution system |
| CAD |
Computer Aided Design |
| CAM |
Content Addressable Memory |
| CAN |
Controller Area Network |
| CCS |
Composite Current Source timing model - used for Static Timing Analysis |
| CDF |
Component Description Format - a format for a celayout in Cadence |
| CDM |
Charged Device Model |
| CFG |
Control Flow Graph |
| CHIPS |
Common Hardware for Interfaces, Processors and System (CHIPS Alliance) |
| CISC |
Complex Instruction Set Computer |
| CIW |
Command Interpreter Window |
| CL |
Combinational Logic |
| CLA |
Carry Lookahead Adder |
| CLB |
Configurable Logic Block |
| CLI |
Command Line Interface |
| CLINT |
Core-Local INTerrupt controller |
| CMI |
Component Model Interface |
| CML |
Current Model Logic |
| CMOS |
Complementary Metal Oxide Semiconductor |
| CNR |
Carrier to Noise amplitude Ratio |
| CoWoS |
Chip on Wafer on Substrate |
| CP |
Charge Pump |
| CPI |
Cycles Per Instruction |
| CPF |
Common Power Format (a Cadence and Si2 tcl-baslanguage for specifying power intent in a chip design) |
| CPU |
Central Processing Unit |
| CSP |
Cloud Service Provider |
| CS |
Chip Select |
| CSCR |
Continuously Scalable Conversion Ratio (has to do with regulators) |
| CTS |
Clock Tree Synthesis |
| CXL |
Compute Express Link |
| CVA6 |
an instantiation of a rocket core |
| CW |
Continuous Wave |
| DAC |
Digital to Analog Converter |
| DAC |
Design Automation Conference |
| DARPA |
Defense Advanced Research Projects Agency |
| DCO |
Digitally Controlled Oscillator |
| DDR |
Double Data Rate |
| decap |
decoupling capacitor |
| DFI |
DDR Phy Interface standard |
| DFF |
D Flip Flop, Data Flip Flop |
| DIBL |
Drain Induced Barrier Lowering |
| DIMM |
Dual In-line Memory Module |
| DL |
Deep Learning |
| DLL |
Delay Lock Loop |
| DLL |
Dynamic Linked Library |
| DMA |
Direct Memory Access |
| DMEM |
Data Memory |
| DMI |
Direct Memory Interface |
| DNN |
Deep Neural Network |
| DOP |
Dilution of Precision - related to GPS |
| DPLL |
Digital Phase Locked Loop |
| DRAM |
Dynamic Random Access Memory |
| DR |
Die Ring |
| DRC |
Design Rule Check |
| DRF |
Display Resource File (.drf extension - Cadence provides for a certain vendor-specific PDK display.drf file to color the layermap in the layout tool) |
| DRM |
Design Rule Manual |
| DRM |
Digital Rights Management |
| DRV |
Data Retention Voltage |
| DSL |
Domain Specific Language |
| DSP |
Digital Signal Processing |
| DTCO |
Design Technology Co-Optimization |
| DUT |
Device Under Test |
| DVE |
Discovery Visualization Environment - old Synopsis waveform viewer |
| DVFS |
Dynamic Voltage and Frequency Scaling |
| ECC |
Error Correction Code |
| ECEF |
Earth Centered Earth Fixed frame - terrestrial cartiasian coordinate system w/Earth at the center |
| ECO |
Engineering Change Order |
| EDA |
Electronic Design Automation |
| EDM |
Electronic Distance Measurement |
| EDP |
Energy Delay Product |
| EEPROM |
Electrically Eraseable Programmable Read-Only Memory |
| EKF |
Extended Kalman Filter |
| ELF |
Executable and Linkable Format |
| EMC |
Electro Magnetic Compatibility |
| EMIB |
Embedded Multi-die Interconnect Bridge |
| EPROM |
Electrically Programmable Read-Only Memory |
| ESD |
Electro Static Discharge |
| ESL |
Equivalent Series Inductance |
| ESP |
Extra Sensory Perception |
| ESR |
Equivalent Series Resistance |
| EU |
Execution Unit |
| EUV |
Extreme Ultra Violet (13.5 nm wavelength) |
| EX |
Execute |
| FASED |
FPGA-Accelerated Simulation and Evaluation of DRAM |
| FCW |
Frequency Control Word |
| FDSOI |
Fully Depleted Silicon On Insulator |
| FEOL |
Front End Of the Line |
| FESVR |
Front End SerVeR |
| FF |
Flip Flop |
| FFT |
Fast Fourier Transform |
| FIFO |
First In, First Out |
| FinFET |
Fin-shaped Field Effect Transistor |
| FIR |
Finite Impulse Response filter |
| FIRRTL |
Flexible Intermediate Representation for RTL (emits tool-friendly, synthesizable Verilog) |
| FLL |
Frequency Lock Loop |
| FLOPS |
FLoating-point Operations Per Second |
| FM |
Frequency Modulation |
| FO4 |
Fan Out of 4 gates |
| FOCoS |
Fan-Out Chip on Substrate |
| FOD |
Fractional Output Divider |
| FOX |
Field OXide |
| FP |
Floating Point |
| FPU |
Floating Point Unit |
| FPGA |
Field Programmable Gate Array |
| FSDB |
Fast Signal DataBase - an open file format fwaveforms |
| FSK |
Frequency Shift Keying |
| FSM |
Finite State Machine |
| FSMD |
Finite State Machine with Datapath |
| FST |
Fast Signal Trace - .fst file format for waveform viewing |
| FTDI |
Future Tech Device Intl (name of a company, but short for a chip that converts RS-232 to SPI, etc.) |
| FTP |
File Transfer Protocol |
| GAA |
Gate All Around transistor |
| GC |
Garbage Collection |
| GCC |
GNU Compiler Collection |
| GCD |
Greatest Common Divisor |
| GCP |
Google Cloud Platform |
| GDB |
GNU DeBugger |
| GDS |
Graphic Data System … a file format originally for the last step for creating photomasks |
| GIDL |
Gate Induced Drain Leakage |
| GIMP |
GNU Image Manipulation Program |
| GNSS |
Global Navigation Satellite System |
| GNU |
GNU is Not Unix |
| GPIO |
General Purpose Input/Output |
| GPP |
General Purpose Processor |
| GPS |
Global Positioning System |
| GPST |
GPS Time |
| GPU |
Graphics Processing Unit |
| GTK |
GIMP Tool Kit |
| GTK |
+ GIMP Took Kit re-write |
| GUI |
Graphical User Interface |
| HAL |
Hardware Abstraction Layer |
| hammer |
Highly Agile Masks Made Effortlessly from RTL |
| HART |
Highway Addressable Remote Transducer (a comm standard for industrial instruments) |
| Hart |
Hardware-managed Thread, a RISC-V concept very similar to “core” in an x86 system. |
| HBM |
High Bandwidth Memory |
| HCSL |
High-speed Current Steering Logic |
| HDL |
Hardware Design Language |
| HDMI |
High Definition Multimedia Inteface |
| HDR |
High Dynamic Range |
| HFF |
High Frequency Fundamental |
| HI |
Heterogeneous Integration |
| HIP |
Hard IP - hard macros to be placed in a layout |
| HLS |
High Level Synthesis |
| HOW |
Hand-Over Word (part of GPS code) |
| HPC |
High Performance Computing |
| HPF |
High Pass Filter |
| HSMC |
High Speed Mezzanine Card |
| HW |
HardWare |
| I2C |
Inter-Integrated Circuit interface |
| IC |
Instruction Count |
| IC |
Integrated Circuit |
| ID |
Instruction Decode |
| IDE |
Integrated Development Environment |
| IDH |
Independent Design House |
| IDM |
Integrated Device Manufacturer |
| IF |
Instruction Fetch |
| IF |
Intermediate Frequency |
| IFS |
Intel Foundry Service |
| ILA |
Integrated Logic Analyzer |
| ILM |
Interface Logic Model - a block in Innovus |
| IMEM |
Instruction Memory |
| InFO_oS |
Integrated Fan-Out on Substrate |
| IO |
Input/Output |
| IoT |
Internet of Things |
| IP |
Intellectual Property |
| IR |
Intermediate Representation |
| ISA |
Instruction Set Architecture |
| ISP |
Image Signal Processor |
| ISP |
In-System Programing |
| ISP |
Internet Service Provider |
| ISR |
Incremental Software Release |
| JDK |
Java Development Kit |
| JEDEC |
Joint Electron Device Engineering Council (a standards organization) |
| JESD |
JEdec StandarD |
| JIT |
Just In Time |
| JSON |
JavaScript Object Notation (data exchange file format) |
| JTAG |
Joint Test Action Group, a standards committee which created a debug protocol and tool |
| JVM |
Java Virtual Machine |
| KOR |
Keep Out Region - used by place-and-route tool |
| LBWIF |
Low Bandwidth Interface |
| LC |
Logic Cell |
| LDF |
Library Definition File (.ldf files are related to .lib files, they’re both timing library formats) |
| LDO |
Low DropOut regulator |
| LED |
Light Emitting Diode |
| LE |
Logic Element |
| LEC |
Logical Equivalence Testing |
| LEF |
Library Exchange Format – an ascii text fidescription of an abstract layout of a cell on a chip. Its MACRO feature is what is pertinent. |
| Liberty |
an ascii text file model (.lib) for static timing analysis. Its CELL feature is what is pertinent. Liberty models are files with a .lib extension. |
| LLVM |
Low Level Virtual Machine |
| LNA |
Low Noise Amplifier |
| LO |
Local Oscillator |
| LPC |
Low Power Coalition |
| LPF |
Low Pass Filter |
| LRU |
Least Recently Used |
| LSB |
Least Significant Bit |
| LSF |
Load Sharing Facility |
| LU |
Latch Up |
| LUT |
Look Up Table |
| LVCMOS |
Low Voltage CMOS signaling |
| LVDS |
Low Voltage Differential Signaling |
| LVPECL |
Low Voltage Positive Emitter-Coupled Logic |
| LVS |
Layout Versus Schematic |
| MC |
Memory Controller |
| MCM |
Multi Chip Module |
| MDF |
Macro Description Format |
| MEM |
MEMory access |
| MESI |
Modified Exclusive Shared Invalid (states of a cache) |
| MIDAS |
Modeling Infrastructure for Debugging And Simulati(a Chisel library) |
| MIM |
capacitor Metal Insulator Metal capacitor |
| MIPI |
Mobile Industry Processor Interface standard |
| ML |
Machine Learning |
| MMIO |
Memory-Mapped Input/Output |
| MMMC |
Multi Mode Multi Corner |
| MMU |
Memory Management Unit |
| MOESI |
Modified Owned Exclusive Shared Invalid (states of a cache) |
| MOM |
capacitor Metal Oxide Metal capacitor |
| MOS |
capacitor Metal Oxide Semiconductor capacitor |
| MOSIS |
Metal Oxide Semiconductor Implementation System, a DARPA-funded multi project wafer service broker system |
| MPW |
Multi Project Wafer |
| MSB |
Most Significant Bit |
| MTAIC |
Multi Tone Active Interference Canceller |
| MUX |
MUltipleXer |
| NC |
Not Connected |
| NCO |
Numerically Controlled Oscillator |
| NDA |
Non-disclosure Agreement |
| NDR |
Non-Default Routing |
| NIC |
Network Interface Controller |
| NLDM |
Non Linear Delay Model - used for Static TimiAnalysis |
| NMEA |
National Marine Electronics Association (GPS daformat) |
| NOC |
Network on Chip |
| NRE |
Non-Recurring Engineering |
| NTF |
Noise Transfer Function |
| NVDLA |
NVidia Deep Learning Accelerator |
| OA |
Open Access (chip industry database format) |
| OASIS |
Open Artwork System Interchange Standard |
| oas |
OASIS file extension |
| OCP |
Open Core Protocol |
| OCS |
Optical Circuit Switching |
| OD |
Oxide Diffusion - mask region for transistor actiarea |
| OO |
Object Oriented |
| OOP |
Object Oriented Programming |
| OOO |
Out Of Order |
| OPB |
On-chip Peripheral Bus |
| OpenOCD |
Open On Chip Debugger |
| OS |
Operating System |
| OTH |
Over The Hierarchy (layout terminology) |
| OTN |
Optical Transport Network |
| OTP |
One Time Programmable |
| PA |
Power Amplifier |
| PAM |
Pulse Amplitude Modulation |
| PAR |
Place And Route |
| PC |
Program Counter |
| PC |
Personal Computer |
| PCB |
Printed Circuit Board |
| PCI |
Express Peripheral Component Interconnect standard |
| PD |
Phase Detector |
| PD |
Physical Design |
| PDF |
Portable Document Format |
| PDF |
Probability Density Function |
| PDK |
Process Design Kit |
| PDMI |
Passive Device Model Interface |
| PDN |
Pull Down Network |
| PDN |
Power Delivery Network |
| PDN |
Power Distribution Network |
| PDS |
Power Distribution System |
| PERL |
Practical Extraction and Reporting Language (scripting language) |
| PFD |
Phase Frequency Detector |
| PG |
Power Grid |
| PGA |
Programmable Gain Amplifier |
| PHP |
PHP: Hypertext Preprocessor |
| PIM |
Processing In Memory |
| PLIC |
Platform Level Interrupt Controller |
| PLL |
Phase Locked Loop |
| PMIC |
Power Management Integrated Circuit |
| PMMU |
Paged Memory Management Unit |
| PMOD |
Peripheral MODule interface |
| PMP |
Physical Memory Protection standard |
| PMT |
Phase Merging Turbo (has to do with switching regulators) |
| PMU |
Power Management Unit |
| PnR |
Place aNd Route |
| pot |
potentiometer |
| PPA |
Performance, Power & Area |
| PPS |
Precise Positioning Service - related to GPS |
| PPS |
Pulse Per Second - related to GPS |
| PRN |
Pseudo Random Noise |
| PRN |
Pseudo Random Number code - identifier for a Gsatellite |
| PSK |
Phase Shift Keying |
| PTW |
Page Table Walker |
| PUN |
Pull Up Network |
| PWM |
Pulse Width Modulation |
| QEMU |
Quick EMUlator |
| QoR |
Quality of Results |
| QSPI |
Quad Serial Peripheral Interface |
| RAM |
Random Access Memory |
| RAS |
Return Address Stack |
| RDL |
Re-Distribution Layer - top layer of routing to a chip’s bumps |
| REPL |
Read Eval Print Loop |
| RF |
Radio Frequency |
| RISC |
Reduced Instruction Set Computer |
| RJ45 |
Registered Jack 45 (a connector type used for ethernet) |
| RMS |
Root Mean Square |
| RNSS |
Radio Navigation Satellite System band - radio frequencies reserved for satellite-based navigation signals |
| RO |
Ring Oscillator |
| RoCC |
Rocket Custom Coprocessor |
| ROM |
Read Only Memory |
| RPM |
Red hat Package Manager |
| RS232 |
Recommended Standard 232 (a wiring standard forserial protocol) |
| RTC |
Real Time Clock |
| RTCM |
Radio Technical Commission for Maritime services - related to GPS |
| RTL |
Register Transfer Language |
| RTOS |
Real Time Operating System (e.g. Zephyr, FreeRTOS) |
| RVV |
RISC-V Vector extension to RISC-V instruction set |
| RX |
Receiver |
| SAIF |
Switching Activity Interchange Format |
| SAR |
ADC Successive Accumulation Register Analog to Digital Converter |
| SAW |
Surface Acoustic Wave |
| SBAS |
Satellite Based Augmentation System - for GPS |
| SBT |
Scala Build Tool |
| SCL |
Source Coupled Logic |
| SCμM |
Single Chip Micro Mote |
| SCVR |
Switched Capacitor Voltage Regulator |
| SD |
Secure Digital (flash memory card) |
| SDC |
Synopsys Design Constraints (file extension for timiand area intent file) |
| SDC |
Standard Design Constraints file |
| SDF |
Standard Delay Format |
| SDR |
Software Defined Radio |
| SDRAM |
Synchronous Dynamic Random Access Memory |
| SER |
Symbol Error Rate |
| SERTL |
SERialized Tile Link |
| SerDes |
Serializer/De-serializer |
| SHA3 |
Secure Hash Algorithm 3 |
| Si2 |
Silicon Integration Initiative |
| SIMD |
Single Instruction Multiple Data |
| SiP |
System in Package |
| SNR |
Signal to Noise Ratio |
| SoC |
System on Chip |
| SODIMM |
Small Outline Dual In-line Memory Module |
| SOI |
Silicon On Insulator |
| SOIC |
Small Outline Integrated Circuit package |
| SOP |
System On Package |
| SOP |
Small Outline Package |
| SPDT |
Single Pole Double Throw switch |
| SPEF |
Standard Parasitic Exchange Format |
| SPI |
Serial Peripheral Interface |
| SRAM |
Static Random Access Memory |
| STA |
Static Timing Analysis |
| STI |
Shallow Trench Isolation |
| SV |
System Verilog |
| SV |
Satellite Vehicle (related to GPS) |
| TCL |
Tool Control Language - for scripting silicon CAD tools |
| TDC |
Time to Digital Converter |
| TDRE |
Transmit Data Register Empty |
| TIA |
Transimpedance Amplifier |
| TileLink |
Open-source chip-scale interconnect standard (comparable to the industry standard protocols AXI/ACE) |
| TK |
ToolKit - open source cross-platform widget toolkfor making GUIs for various languages |
| TLB |
Translation Lookaside Buffer |
| TLF |
Timing Library Files - .tlf is a file extension that Cadence Innovus understands |
| TMA |
Tapeout Manufacturing Assurance (mock tape-in number) |
| TNS |
Total Negative Slack |
| toml |
Tom’s Obvious Minimal Language (file format for configuration files) |
| TOS |
Top Of Stack |
| TPU |
Tensor Processing Unit |
| TSI |
Tethered Serial Interface, or more commonlSerialized TileLink |
| TSMC |
Taiwan Semiconductor Manufacturing Corporation |
| TSV |
Through Silicon Via |
| TTFF |
Time To First Fix - for GPS |
| TX |
Transmitter |
| TCXO |
Temperature Compensated Xtal Oscillator |
| UART |
Universal Asynchronous Receiver Transmitter |
| UCIe |
Universal Chiplet Interconnect express (interconnect standard) |
| UPF |
Unified Power Format (a Synopsys and Siemens Mentor tcl-based language for specifying power intent in a chip design) |
| USB |
Universal Serial Bus |
| USRP |
Universal Software Radio Peripheral |
| UTC |
Universal Time Coordinated - related to GPS |
| UV |
Ultra-Violet |
| UVM |
Universal Verification Methodology |
| VCD |
Value Change Dump |
| VCO |
Voltage Controlled Oscillator |
| VCS |
Verilog Compiler and Simulator (a Synopsis tool) |
| VCU |
Video transCoding Unit |
| VCU118 |
a part number for a Xilinx FPGA board widely used BWRC |
| VCDL |
Voltage Controlled Delay Line |
| VFC |
Voltage to Frequency Converter |
| VGA |
Variable gain amplifier |
| VHDL |
VHSIC Hardware Description Language |
| VHSIC |
Very High Speed Integrated Circuit |
| VLIW |
Very Long Instruction Word |
| VLSI |
Very Large Scale Integration |
| VM |
Virtual Memory |
| VML |
Voltage Mode Logic |
| VR |
Voltage Regulator |
| VRM |
Voltage Regulator Module |
| VXU |
Vector eXecution Unit |
| WAAS |
Wide Area Augmentation System (ground stations augmenting GPS) |
| WB |
Write Back to register |
| WNS |
Worst Negative Slack |
| WSN |
Wireless Sensor Network |
| Xbar |
crossbar switch |
| XiP |
eXecute in Place |
| YAML |
Yet Another Markup Language |
| yml |
YAML file extension |